1. Field of the Invention
The present invention relates generally to clock signal generation, and more specifically to generating clock signals exhibiting zero deterministic jitter.
2. Description of the Related Art
Most of today's digital systems are synchronous systems built of components operating according to one or more clock signals, which are used to coordinate the operation of the various components. Oftentimes, clock signals are generated by circuitry configured on integrated circuits (ICs), which may or may not also include other system components. On an IC (chip), an accurate clock reference is usually generated with the use of an analog phase-locked loop (PLL) locked to a crystal operating at a specified frequency. The PLL can be used to easily create clock signals having frequencies that are multiple(s) of the crystal frequency. In many cases frequency synthesizers can be used to generate other frequencies without requiring an additional crystal and/or analog PLLs. In a digital frequency synthesizer (DFS), accurate frequency is achieved by performing time averaging. The output frequency can have a cycle time of T or T±Δ, where Δ is the minimum step-size that can cause deterministic jitter.
Jitter is typically defined as the undesired deviation from true periodicity of a nominally periodic signal, often in relation to a reference clock source. Jitter can be present in characteristics such as the frequency of successive pulses, the signal amplitude, or the phase of periodic signals, and is a significant and undesired factor in the design of almost all communications links (e.g., USB, PCIe, SATA, OC-48). In general, jitter generated in digital systems ultimately reduces signal quality. For example, in the case of digital video transmission devices, jitter in a transmission path or during video clock regeneration can result in phase noise during the decoding of video signals, which reduces image quality. In high performance applications, such as PCIe/USB/MOST, any factor causing deterministic jitter (e.g. the minimum step-size for the DFS mentioned above) can make the jitter specification hard or impossible to meet, oftentimes resulting in compromised performance and in extreme cases, system malfunction.
Therefore, various solutions have been implemented over the years to minimize or eliminate jitter. One possible solution is based on an analog fractional N frequency synthesizer that is a modified version of a PLL based synthesizer, with the integer frequency divider replaced by a fractional frequency divider. Since an analog PLL is still required, this solution requires more power and additional area on the IC. Another solution features a flying adder that uses time averaging to generate different frequencies. One example of this solution is shown in FIG. 1. The output of a voltage-controlled oscillator (VCO) is provided to a multiplexer 102, which receives a 10-bit select signal from register 106. The select signal is generated by adding a current value of the content of register 106 to a frequency value input in adder 108, clocking the output of register 106 with the clock signal output from multiplexer 102. The output clock signal (Z) is then provided from the output of D Flip Flop 104. In this solution, the output deterministic jitter is limited by the minimum step-size. One way to minimize jitter is to use a smaller step-size Δ. Yet, this still requires more power and additional IC area, which can be limited by the fabrication process, among other things.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.